1. Field of Invention
Embodiments of the invention relate generally to memory, such as memory devices and memory systems, and more particularly, to memory having internal processors.
2. Description of Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light and not as admissions of prior art.
Electronic systems typically include one or more processors, which may retrieve and execute instructions, and store (e.g., retire) the results of the executed instruction, such as instructions to store the results to a suitable location. A processor may generally use arithmetic logic unit (ALU) circuitry to execute instructions, such as arithmetic and logic operations, on data, such as one or more operands. For example, the ALU circuitry may add, subtract, multiply, or divide one operand from another, or may subject one or more operands to logic operations, such as AND, OR, XOR, and NOT logic functions. A processor may execute instructions having different degrees of complexity, and different instructions may involve inputting the operand(s) through the ALU circuitry in one or multiple clock cycles.
A number of components in the electronic system may be involved in directing a set of instructions to the ALU for execution. In some devices, the instructions may be generated by a controller, or some other suitable processor in the electronic system. Data (e.g., the operands on which the instructions will be executed) may be stored in a memory device (e.g., a memory array) that is accessible by the ALU. The instructions and data may be retrieved from the memory device and sequenced and/or buffered before the ALU begins to execute instructions on the data. Furthermore, as different types of operations may be executed in one or multiple clock cycles through the ALU, intermediate results of the instructions and/or data may also be sequenced and/or buffered.
Typically, a processor (e.g., the ALU circuitry) may be external to the memory array, and data is accessed via a bus between the processor and the memory array to execute a set of instructions. As processing speed may be limited by the bandwidth of the bus, processing performance may be improved in a processor-in-memory (PIM) device, where the processor is implemented internal to a memory (e.g., directly on the memory device), conserving time and power in processing. Furthermore, processing power may also be improved by writing, reading, sequencing, buffering, and executing instructions and/or data substantially simultaneously for different instructions, or different parts (operations) of an instruction.